Generally, in a DRAM (Dynamic Random Access Memory), an operation mode and/or various parameters, such as CAS (column address strobe) latency and burst length, may be set by a MRS (Mode Register Set) command. In semiconductor memory devices, a rank refers to a plurality of DRAMs controlled by a chip selection signal. A rank or a plurality of ranks can be installed in a memory system.
DRAMs belonging to a same rank may share buses through which chip selection signals, commands, and address signals are transmitted. Accordingly, if a MRS command is transmitted through an address bus, all DRAMs belonging to a corresponding rank may be set to the same operation mode. However, operation modes and/or parameters of DRAMs belonging to the same rank should be individually controlled.
FIG. 1 is a block diagram of a conventional memory system 100. Referring to FIG. 1, the memory system 100 includes a memory controller 10 and a memory module 20. The memory module 20 includes a plurality of memory devices 30. The memory devices 30 may be controlled according to a chip selection signal (not shown). That is, the memory module 20 shown in FIG. 1 includes a rank. Each memory device 30 receives a clock signal CK and a command address signal CA from the memory controller 10. Also, each memory device 30 receives/transmits data DATA1 through DATA9 and a data strobe signal (not shown) from/to the memory controller 10.
FIG. 2 is a block diagram of an individual memory device 30 shown in FIG. 1. Referring to FIG. 2, the memory device 30 includes a command decoder 31, an internal clock generator 32, a data input/output buffer 34, and a memory cell array 36. The command decoder 31 receives and decodes a command address CA from the memory controller 10 and generates an internal command. Here, the internal command may be a write command IWRITE, a read command IREAD, or a MRS command IMRS, according to a received command address CA. The internal clock generator 32 generates an internal clock signal ICLK in response to a clock signal CK and the internal command IMRS, IREAD, or IWRITE.
The data input/output buffer 34 stores data DATA input with a data strobe signal DQS, as internal data IDATA, in the memory cell array 36, in response to the internal clock signal ICLK. The data input/output buffer 34 outputs internal data IDATA stored in the memory cell array 36 to an external memory controller 10 in response to the internal clock signal ICLK.
Although the memory devices 30 receive data IDATA from the memory controller 10 at the same time, the memory devices 30 may respectively receive a clock signal CK at different times because the respective memory devices 30 may sequentially receive the clock signal CK per a delay T. As a result, the respective memory devices 30 may generate internal clock signals ICLK at different times, in response to the clock signal CK. Since the respective memory devices 30 generate the internal clock signals ICLK at different times, the data IDATA may also be stored and/or output at different times.
FIG. 3 is a timing diagram illustrating a data read operation performed by the memory system 100 shown in FIG. 1. Referring to FIG. 3, data read operations performed by a first memory device M1, a fifth memory device M5, and a ninth memory device M9 of the memory module 20 will be described. As shown in FIG. 3, the first memory device M1, the fifth memory device M5, and the ninth memory device M9 receive clock signals CK1, CK5, and CK9, at different times, respectively.
Accordingly, the memory devices M1, M5, and M9 generate first, fifth, and ninth internal clock signals ICLK1, ICLK5, and ICLK9, at different times, respectively. In FIG. 3, the first internal clock signal ICLK1 may be generated earlier than the fifth internal clock signal ICLK5 by a period 4T, and the fifth internal clock signal ICLK5 may be generated earlier than the ninth internal clock signal ICLK9 by a period 4T.
Referring to FIG. 3, when data is read, internal data IDATA stored in the memory cell array 36 may be output in synchronization with the internal clock signal ICLK1, ICLK5, or ICLK9. As shown in FIG. 3, first data DATA1, fifth data DATA5, and ninth data DATA9 may be respectively output at different times. In other words, the first, fifth, and ninth data DATA1, DATA5, and DATA9 may have a data skew DSK.
FIG. 4 is a timing diagram illustrating a data write operation performed by the memory system 100 shown in FIG. 1. Referring to FIG. 4, the first memory device M1, the fifth memory device M5, and the ninth memory device M9 may receive clock signals CK1, CK5, and CK9 at different times, respectively.
Accordingly, the memory devices M1, M5, and M9 may generate first, fifth, and ninth internal clock signals ICLK1, ICLK5, and ICLK9 at different times, respectively. In FIG. 4, the first internal clock signal ICLK1 may be generated earlier than the fifth internal clock signal ICLK5 by a period 4 T, and the fifth internal clock signal ICLK5 may be generated earlier than the ninth internal clock signal ICLK9 by a period 4 T. When data is written, data DATA received from the outside may be stored in the memory cell array 36 in synchronization with the internal clock signal ICLK1, ICLK5, or ICLK9. Referring to FIG. 4, first internal data IDATA1, fifth internal data IDATA5, and ninth internal data IDATA9 may be generated at different times. That is, the internal data IDATA1, IDATA5, and IDATA9 stored in the memory cell array 36 may have data skew DSK.
Because the memory devices 30 of the memory module 20 shown in FIG. 1 may receive a clock signal CK at different times, skew may be generated when data is stored or read. Accordingly, synchronization of internal clock signals ICLK from the memory devices 30 may be desired.